Curriculum
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PROFESSIONAL ACTIVITY
- Since september 1st, 2023 – Currently on leave from Univ. of Ferrara. Reader in Advanced Processor Technologies in the Department of Computer Science at University of Manchester (United Kingdom).
His research mission is to stay at the forefront of system innovation by means of a cross-layer approach that leverages the enabling features of emerging computing and interconnect technologies.
His current interests range from neuromorphic computing to analog accelerators, and from asynchronous networks-on-chip to silicon nanophotonic networks. In particular:
- Neuromorphic computing platforms
- Multi-tenant edge computing platforms
- Design methods for analog deep learning accelerators
- Reliability analysis and fault-tolerance of deep learning hardware
- Silicon nanophotonic networks
Fact sheet:
- Roughly 200 peer-reviewed scientific papers
- 5 best paper awards, 3 best paper award nominations
- H-index: 30 (Source: Scopus)
- 24 officially advised or co-advised PhD students.
- More than 3 Million euros of autonomous fund raising
- Design of 2 electronic test-chips (GALS interfaces in 40nm and neuromorphic processor in 22nm) and of 2 photonic integrated circuits (small-scale optical network-on-chip prototypes).
- Since 2023, Teaching commitments at University of Manchester, BSc in Computer Science:
- COMP25212 - System Architecture
- COMP32211 – Implementing Systems-on-Chip
- From 2020 to 2023 –Associate Professor in Electrical Engineering at University of Ferrara (Italy).
- In 2017, National Habilitation to take on a Full Professor role in Electrical Engineering in Italian universities.
- In 2017, National Habilitation to take on a Full Professor role in Computer Science and Engineering in Italian universities.
- In 2014, National Habilitation to take on an Associate Professor role in Computer Science and Engineering in Italian universities.
- In 2013, National Habilitation to take on an Associate Professor role in Electrical Engineering in Italian universities.
- From 2005 to 2020 –Assistant Professor in Electrical Engineering at University of Ferrara (Italy).
- From 2005 to 2023. Teaching commitments at University of Ferrara within the Master in Electronics for ICT, the generalist Bachelor Program in Electronics and Informatics Engineering, and the Bachelor Program in Informatics. Taught course units:
- Laboratory of SystemC-based Virtual Prototyping
- Laboratory of Assembly programming
- Electronic Instrumentation and Measurements
- Laboratory of Electronic Measurements
- From 2023, member of the Advisory Board for the PhD in Computer and Data Science for Technological and Social Innovation at University of Modena-Reggio Emilia (Italy).
- From 2023, responsibilities held at University of Manchester:
- PhD cohort advisor
- Member of the panel for the Research Review Exercise in preparation for the REF evaluation in 2029.
- In 2020, member of the steering committee of the PhD in “Arquitecturas y Tecnologías Eficientes en Computación”, at Universidad Catolica de Murcia (Spain)
- From 2009 to 2023. Bertozzi has been member of the steering committee for the PhD program in Engineering Sciences at University of Ferrara.
- 2010-2023, Bertozzi was Erasmus Coordinator for the ICT field at University of Ferrara:
- Establishment of a Framework Agreement for research and teaching with Universidad Catolica San Antonio de Murcia (Spagna).
- Memorandum of Undertanding for an international student exchange program with Shibaura Institute of Technology (Japan).
- From 2018 to 2023, Bertozzi was U. of Ferrara’s delegate to the General Assembly of the ARTEMIS Industry Association.
- Present – Editor-in-Chief for the Journal on Low Power Electronics (MDPI).
- Present - Member of the Editorial Board for the IEEE Transactions on Computers, for the IET CDT (Computers and Digital Techniques) Journal and for the Springer DAEM (Design Automation for Embedded Systems) Journal.
- Reviewer for international scientific Journals (IEEE Transactions on Circuits and Systems, IEEE Design & Test, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Computers, IEEE Transactions on VLSI, IEEE Transactions on Multi-scale Computing Systems, ACM Journal on Emerging Technologies in Computing, ACM Computing Surveys, ACM Transactions on Embedded Computing Systems, ACM TACO, Transactions on Parallel and Distributed Processing Systems, IET Computer and Digital Techniques, Embedded Systems Letters, Computer Architecture Letters, Transactions on Industrial Informatics, the Hindawi VLSI Journal, Journal of System Architecture, Microelectronics Journal, Journal of Electronic Imaging, Transactions on Mobile Computing, the Computer Journal, Journal of Supercomputing, Journal of Parallel and Distributed Computing).
- Member of the Technical Programme Committee for international scientific conferences: Design, Automation and Test in Europe (DATE) Conference, Design Automation Conference (DAC), Int. Symp. on Networks-on-Chip, International Conference on Circuits and Systems (ISCAS), Int. Conference on High-Performance Computing and Simulation (HPCS), Int. Symposium on Asynchronous Circuits and Systems (ASYNC), Int. Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS), International Symposium on Systems-on-Chip, Euromicro Conference on Digital System Design (DSD), GLSVLSI Conference, INA-OCMC Workshop, the NoCArch Workshop, Eurasip JES, CMP-MSI Workshop, Int. Symp. on Embedded Multi/Manycore SoCs (MCSoC), Int. Conf. on Electronics, Circuits and Systems (ICECS), Int. Conference on Computer-Aided Design (ICCAD), Int. Conf. on Next Generation of Circuits and Systems (NGCAS), DATE PhD Forum.
- Serving as Expert for the European Union, for the evaluation of both FP7 and Horizon2020 projects. Up to date, 2 project review meetings (including a final review meeting) have been managed in the context of the Future Emerging Technologies (FET) program, to assess project ENTRA (FP7-318337) from 2013 to 2016.
- Member of the Hipeac Network-of-Excellence (NoE), the European Network on High Performance, Edge and Cloud Computing. Active contribution to the achievement of the NoE goals through the following activities:
- Organization of the INA-OCMC Workshop yearly (9 editions overall, till 2015), formerly co-located with the Hipeac Conference. From 2016 to 2019, INA-OCMC has evolved into the AISTECS Workshop on emerging interconnect solutions for large-scale systems.
- 2015-2017. Leader of the “Research at School” outreach initiative, aiming at familiarizing high-school students with the research experience, in order to make science education and careers attractive for young people. Collaboration with the Department of Pedagogy at University of Verona (Italy).
- 2003-2004. Post-Doc at University of Bologna (Italy).
Technical leader of projects in the Multi-processor System-on-Chip (MPSoC) domain under the scientific lead of Prof. Luca Benini. Major depth in the following research topics:
- Mixed-timing architectures.
- Design space exploration of MPSoCs.
- Allocation and scheduling of MPSoCs.
- Task migration support in embedded MPSoC architectures.
- Programming models for MPSoCs.
- Past Teaching commitments. Course units:
- From 2003 to 2005. Multimedia Systems at the Faculty of Mathematical, Physical and Natural Sciences at University of Urbino (Italy).
- 2009. Master course at Networks-on-Chip: an Implementation Perspective at Universidad Politecnica de Valencia (Spain).
- 2014. Lecture on networks-on-chip at the MPSoC Winter School on Design, Programming and Applications of Multi-Processor Systems on Chip, held in Tunis.
- From 2012 to 2015. Teaching commitment at ALaRI (Advanced Learning and Research Institute at Università della Svizzera Italiana, Switzerland), in the Master Program in Embedded Systems. Course taught: Networks-on-chip (shared with Prof. Luca Benini).
- From 2014 to 2016. Yearly teaching commitment at ENSI (École Nationale des Sciences de l'Informatique) Tunis, in the Master Program in Embedded Systems. Course taught: Networks-on-chip and its Emerging Applications.
- Wide conference organization experience
- Special Session chair at the IEEE International Symposium on Circuits and Systems 2025, London (UK).
- Special Session chair at the 28th Int. Symposium on Asynchronous Circuits and Systems 2023, Bejing (China).
- Publication chair for the VLSI-SoC Conference 2018, Verona (Italy).
- Tutorial co-organizer at the International Symposium on Circuits and Systems (ISCAS) 2018, Florenz (Italy). Title: “From Emerging Applications, the Quest for Asynchronous Circuits and Systems”, co-organized with Steve Nowick (Columbia University).
- Special Session co-organizer at the IEEE VLSI Test Symposium 2018 in San Francisco (USA). Title: “Overcoming Reliability and Energy-Efficiency Challenges with Silicon Photonics for Future Manycore Computing”, co-organized with Sudeep Pasricha (Colorado State University).
- Special Session co-organizer at the first NGCAS Conference (September 2017, Genoa) on Asynchronous and GALS design, with prof. Steve Nowick (Columbia Univ.)
- General chair of the INA-OCMC Workshop, co-located with the Hipeac conference, in 2010, 2011, 2012 and 2013.
- Program chair for the network-on-chip track at the Design Automation and Test in Europe Conference (DATE) in 2010, 2011 and 2012 (max. 3 years allowed).
- Full-day Tutorial at the Hipeac Conference in Pisa (Italy, 2010). Title: “Networks-on-Chip: the New Frontier for Interconnection Networks”.
- Program chair for the 3rd International Workshop on Interconnection Networks: On-Chip, Multi-Chip (INA-OCMC) 2009, Cyprus.
- Program chair for the 2nd Int. Symposium on Networks-on-Chip 2008, Newcastle (UK).
- Full-day Tutorial at the Int. Symposium on Systems-on-chip in Tampere (Finland, 2005). Title: “The Status of the Network-on-Chip Revolution: Design Methods, Architectures and Silicon Implementation”.
- Keynote speaker experience
- 2nd Int. Conf. on Design, Test and Technology of Integrated Systems (DTTIS) 2024. Title: “Overcoming the Communication Bottleneck in Neuromorphic Computing Systems”.
- 15th International Workshop on Network-on-Chip Architectures (NOCARC22) 2022. Title: “Ultra-Low Power and Flexible Asynchronous Interconnect Technology for Large-Scale Neuromorphic Computing.”
- 4th Int. Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS 2019), in conjuction with the Hipeac Conference 2019. Title: “Emerging Silicon Nanophotonic Networks: Time to Bridge the Gap with System Designers”.
- 8th Int. Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip (INA-OCMC 2014), in conjunction with the Hipeac Conference 2014. Title: “Networks-on-Chip as a Stepping Stone into the Nex Generation of Homogeneous Manycores: When Homogeneous Becomes Heterogeneous”.
- 3rd Workshop on Communication Architecture for Scalable Systems, in conjunction with the IEEE Int. Parallel and Distributed Processing Symposium, 2013. Title: “Optical Interconnection Networks on the Way from Concept to Technology”.
- Guest Editor Experience
- MDPI Micromachines. Special Issue on: Networks-on-Chip Again on the Rise: from Emerging Applications to Emerging Technologies. 2021. Guest Editorial in Micromachines 2021, 12, 1570.
- Design Automation for Embedded Systems 18 (3-4). Special Issue on: The Fast Evolving Landscape of On-Chip Communication. Guest Editorial on page 119-120. 2014.
- IET Computer and Digital Techniques 3 (5). Special Issue on: Networks-on-Chip. Guest Editorial on page 395-397. 2009.
- Int. Journal on VLSI Design, Special Issue on: Networks-on-Chip: Emerging Research Topics and Novel Ideas. Guest Editorial on page 26454:1-26454:3. 2007.
- Examiner for final PhD oral dissertations:
- Invited speaker and panelist experience
- 2025. Invited Talk at the 1st TAICHIP Winter School at IHP Microelectronics (Germany). Title: “Asynchronous Interconnect Technology for Neuromorphic Computing”.
- 2024. Invited Talk at the Huawei Thames Summit 2024. Title: “Cross-Layer Reliability Analysis of Deep Learning Accelerators.”
- 2023. Invited Talk at the “Int. Workshop on Memory-Centric Computing 2023”.
Title: “Design Technology for the Cross-Layer Analysis of Analog Accelerators based on Resistive Crossbar Arrays”.
- 2022. Invited talk at Hewlett Packard Enterprise (USA). Title: “Silicon Nanophotonic Networks: from Research Concept to Interconnect Technology”.
- 2022. Invited talk at the IEEE Int. Conference on Artificial Intelligence Circuits
and Systems (AICAS). Title: “An Asynchronous Soft Macro for Ultra-Low Power
Communication in Neuromorphic Computing”.
- 2022. Instructor at the 18th Int. Summer School of Advanced Computer Architecture and Compilation for High-Performance Embedded Systems (ACACES). Title of the online course (4 lectures): “Networks-on-chip for Emerging Systems and Technologies: no Business as Usual”. Appreciation rate: 4/5.
- 2021. Panelist at the NoCArc Workshop. Panel title: “Machine Learning and Networks-on-Chip”.
- 2020. Instructor at the 16th Int. Summer School of Advanced Computer Architecture and Compilation for High-Performance Embedded Systems (ACACES). Title of the online course (3 lectures): “The Latest News on NoCs: from Advanced Use Cases to Emerging Technologies”. Appreciation rate: 4/5.
- 2019. Panel Moderator at OPTICS 2019, co-located with DATE 2019. Opening Talk: “Bringing On-Chip Optical Interconnects into the Real World”.2019. Panel Moderator at OPTICS 2019, co-located with DATE 2019. Opening Talk: “Bringing On-Chip Optical Interconnects into the Real World”.
- 2018. Invited Talk at D43D Workshop, co-located with the LETI Innovation Days. Title: “Toward a Top-Down Synthesis Methodology for 3D-Stacked Wavelength-Routed Optical NoCs”.
- 2018. Invited Talk at IHP Microelectronics. Title: “Emerging Interconnect Technologies for the New Golden Age of Computing: Time to Bridge the Gap with System Designers”.
- 2018. Invited Talk at OPTICS 2018. Title: “Toward a Cross-Layer Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip”.
- 2018. Panelist at OPTICS 2018, in a Panel Discussion on Silicon Photonics.
- 2018. Invited Talk at GLSVLSI 2018. Title: “Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D Architectures”.
- 2018. Invited Talk at VTS 2018. Title: “Toward a Cross-Layer Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip”.
- 2018. Invited Talk at TU Munich, Department of Electrical Engineering. Title: “Towards Elastic HW/SW Learning Systems at the Edge – an Interconnect-Centric Approach”.
- 2018. Invited Talk at ISCAS Tutorial AM7 on “the Quest for Asynchronous Circuits and Systems”. Title: “Cost Effective Asynchronous Interconnect Technology for Ultra-Low Power Systems”.
- 2017. Invited Talk at NEWCAS 2017. Title: “Concurrent Network-on-Chip Lifetime Testing Through Selective Disconnection of its Communication Channels”.
- 2017. Seminar held at TU Munich. Title: “Design Automation Beyond its Electronic Roots: Toward a Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip”.
- 2017. Invited Talk at CMOS Emerging Technologies Conference in Warsaw. Title: “EDA Beyond its Electronic Roots: Toward a Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip”.
- 2017. Invited Talk at Politecnico di Torino (Italy). Title: “Interconnection Networks: a Stepping Stone into the Next-Generation of Parallel Computing Systems”.
- 2017. Invited Talk at University of Notre Dame (Indiana). Title: “Network-on-Chip-Enabled Flexible Partitioning and Isolation of Multi-Workload Homogeneous Manycores”.
- 2017. Invited Talk at the OPTICS Workshop, co-located with DATE 2017. Title: “Design Automation Beyond its Electronic Roots: Toward a Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip”.
- 2017. Invited Talk at NGCAS 2017. Title: “Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip”.
- 2016. Invited Talk at the Dagstuhl meeting on Adaptive Isolation for Predictability and Security. Talk title: “Network-on-Chip-Assisted Adaptive Partitioning and Isolation Technology for "Dynamic" Homogeneous Manycores”.
- 2016. Invited Talk at the OPTICS Workshop, co-located with DATE 2016. Title: “Layout Design of Wavelength-Routed Optical NoCs: the Global Picture”.
- 2016. Invited Talk at TU Wien (Austria). Title: “Networks-on-Chip: a Stepping Stone into the Next Generation of Parallel Computing Systems”.
- 2015. Invited Talk at Intel (Hillsboro, USA) on Oct. 9th. Title: “Asynchronous Bundled-Data NoCs: from Research Concept to Interconnect Technology”.
- 2015. Invited Talk at the Workshop on the Design for 3D Silicon Integration, co-located with the LETI Innovation Days. Title: “Addressing the System-Ability Gap of Optical Networks-on-Chip in 3D Manycore Systems Through Cross-Layer Design and Benchmarking Methods”.
- 2015. Invited Talk at the Int. Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS). Title: “Towards a Vertically Integrated Synthesis Flow for the Design of Wavelength-Routed Optical NoCs”.
- 2015. Panelist at the Int. Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS). Title: “The Last Mile? Remaining Challenges in Optical Interconnects”.
- 2015. Invited Talk at the Hipeac Conference 2015, main conference track. Title: “FLARES: an Aging-Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories”.
- 2014. Invited Talk at the IMS3TW Workhop. Title: “Integrated Cross-Layer Solutions for Enabling Silicon Photonics into Future Chip Multiprocessors”.
- 2013. Invited Talk at the "Shonan Meeting" (the japanese Dagstuhl meeting) organized by the National Institute of Informatics, Tokyo. Title: “Further Optimizing (Multi-) Synchronous Design or Going Straight for Emerging Technologies?"
- 2013. Panelist at the "Shonan Meeting" organized by NII, Tokyo, Japan. Title: "Interconnects for Many-Cores: the Embedded Computing Landscape".
- 2013. Invited Talk at the International System-on-Chip Conference, Irvine (USA). Title: “Optical Interconnect Technology for 3D Stacked Multi- and Many-Core Systems: When, Where and How”.
- 2013. Invited Talk at the HIPEAC Computing System Week, Tallinn (Estonia), within the thematic session "Silicon Photonics for Next Generation Computing Systems". Title: "Optical Interconnection Networks on the Way from Concept to Technology".
- 2013. Invited Talk at Design for 3D Silicon Integration Workshop, co-located with the LETI Innovation Days. Title: "Illuminating Future 3D Architectures with Optical Networks-on-Chip".
- 2013. Invited Talk at the Int. Symp. on Photonics and Electronics Convergence, Tokyo (Japan). Title: “Crossbenchmarking an Optical Network-on-Chip with an Aggressive Electrical Baseline with Physical Layer Analysis”.
- 2012. Invited Talk at the Green Computing Conference 2012, USA. Title: “Power Efficiency of Switch Architecture Extensions for Fault-Tolerant NoC Design”.
- 2012, Invited Talk at the CMOS Emerging Technologies Workshop 2012, Whistler (Canada). Title “A Cross-Layer Approach to the Design and Evaluation of Optical Network-on-Chip Topologies”.
- 2011. Invited Talk at the CMOS Emerging Technologies Workshop 2011, Whistler (Canada). Title “Overcoming the Clocking Concern in MPSoCs: from the GALS concept to mature GALS technology”.
- 2010. Invited Talk at the CMOS Emerging Technologies Workshop 2010, Whistler (Canada). Title “The Latest from the Network-on-Chip Revolution”.
- 2009. Invited Talk given at Micron Design Center, Padova (Italy). Title: "MPSoC Research at University of Ferrara" Industrial dissemination of research outcomes.
- 2009. Invited Talk given at the Interconnect Cluster Meeting of the Hipeac Network-of-Excellence in Wroclaw (Poland). Title: "A GALS Design Methodology for Flexible and Cost-Effective Networks-on-Chip".
- 2009. Invited Talk given at NEC headquarter in Tokyo, Japan. Title of presentation “Designing Networks-on-Chip with Technology-Awareness Across All Layers of the Design Hierarchy”.
- 2009. Invited Talk given for STMicroelectronics - Grenoble during the joint meeting with University of Ferrara. Title: “Network-on-Chip Technology for Multiprocessor Systems-on-Chip Communication”.
- 2009. Invited Talk given at the Interconnect Cluster Meeting of the Hipeac Network-of-Excellence, Paris. Title: "A Silicon Aware Design Platform for Nanoscale Networks-on-Chip"
- 2008. Invited Talk given at NEC America Laboratories, Princeton, New Jersey (USA). Title of the presentation: “Designing, Interfacing and Interconnecting Hardware and Software Components in Highly Integrated MPSoC Platforms”.
- 2008. Invited Talk given at the Hipeac interconnect cluster meeting in Goteborg (Sweden): “Performance of NoC Topologies under Synchronization Intensive Traffic Patterns”.
- 2008. Invited Talk given at the Hipeac interconnect cluster meeting in Barcellona (Spain): “Network-on-Chip Topologies for 64-Tile General Purpose MPSoC Platforms”.
- 2007. Invited Talk given at the Hipeac interconnect cluster meeting in Cambridge (UK): “Guiding Physical Synthesis of NoC Topologies Through Transaction Level Simulation”.
- 2007. Invited Talk given at STMicroelectronics, Catania (Italy). Title: “Capturing the Interaction of the Communication, Memory and I/O Sub-systems in Memory-Centric Industrial MPSoC Platforms”.
- 2005. Invited Talk in the tutorial on networks-on-chip at the International Symposium on System-on-Chip in Tampere (Finland): “The road to NoCs: Evolving Bus Protocols and Topologies”, “Principles of Interconnection Networks”, “Overview of Network-on-Chip Architectures”.
- 2005. Invited Talk at Intel Haifa (Israel) on “Communication-centric low-power architectures for multi-processor systems-on-chip”.
- 2003. Invited Talk at University of California-Berkeley (USA) on “Analyzing the MPSoC design Space: The MPARM environment” within the Electronic Systems Design Seminar series.
- 2003. Seminar held at Stanford University (USA), on “Analyzing the MPSoC design Space: The MPARM environment”.
FUNDED PROJECTS AND PERSONAL ROLE
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SCIENTIFIC PRODUCTION Bertozzi has published (as of february 2025):
- H-index: 30
- Citations: 4215
- Citing documents: 3136
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