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Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach
Bellodi, Elena; Bertozzi, Davide; Bizzarri, Alice; Favalli, Michele; Fraccaroli, Michele; Zese, Riccardo     dettagli >>

Atto di Convegno (Proceedings)
Institute of Electrical and Electronics Engineers Inc., 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
pp: 171-178, Anno: 2023

The challenge of classification confidence estimation in dynamically-adaptive neural networks
Dall’Occo, Francesco; Bueno-Crespo, Andrés; Abellán, José L.; Bertozzi, Davide; Favalli, Michele     dettagli >>

Atto di Convegno (Proceedings)
Springer, Embedded Computer Systems: Architectures, Modeling, and Simulation. 21st International Conference, SAMOS 2021, Virtual Event, July 4–8, 2021, Proceedings
Vol. 13227, No. 1, pp: 505-522, Anno: 2022

Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study
Veronesi, A.; Dall'Occo, F.; Bertozzi, D.; Favalli, M.; Krstic, M.     dettagli >>

Atto di Convegno (Proceedings)
Institute of Electrical and Electronics Engineers Inc., Proceedings - 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022
pp: 142-147, Anno: 2022

A scalable bidimensional randomization scheme for tlc 3d nand flash memories
Favalli, M.; Zambelli, C.; Marelli, A.; Micheloni, R.; Olivo, P.     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
MICROMACHINES
Vol. 12, No. 7, pp: 759-1-759-14, Anno: 2021

A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices
Dalpasso, Marcello; Bertozzi, Davide; Favalli, Michele     dettagli >>

Atto di Convegno (Proceedings)
IEEE, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
Vol. 2018, No. 1, pp: 297-300, Anno: 2018

A Built-In Self-Testing Framework for Asynchronous Bundled-Data NoC Switches Resilient to Delay Variations
Miorandi, Gabriele; Bertozzi, Davide; Favalli, Michele; Celin, Alberto     dettagli >>

Atto di Convegno (Proceedings)
Institute of Electrical and Electronics Engineers Inc., Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) 2016
pp: 113-120, Anno: 2016

Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults
Favalli, Michele; Dalpasso, Marcello     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
IEEE TRANSACTIONS ON COMPUTERS
Vol. 65, No. 3, pp: 706-715, Anno: 2016

Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Favalli, Michele; Marcello, Dalpasso     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
JOURNAL OF ELECTRONIC TESTING
Vol. 30, No. 1, pp: 41-55, Anno: 2014

Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits
Lorenzo, Valenti; Favalli, Michele; Marcello, Dalpasso     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
IET COMPUTERS & DIGITAL TECHNIQUES
Vol. 8, No. 2, pp: 83-89, Anno: 2014

A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs
Ghiribaldi, Alberto; Ludovici, Daniele; F., Trivino; Strano, Alessandro; J., Flich; J. L., Sanchez; F., Alfaro; Favalli, Michele; Bertozzi, Davide     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS
Vol. 12, No. 4, pp: 106:1-106:29, Anno: 2013

Power efficiency of switch architecture extensions for fault tolerant NoC design
Ghiribaldi, Alberto; Strano, Alessandro; Favalli, Michele; Bertozzi, Davide     dettagli >>

Atto di Convegno (Proceedings)
IEEE, Green Computing Conference (IGCC), 2012 International
pp: 1-6, Anno: 2012

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits
Mele, Santino; Favalli, Michele     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Vol. 30, No. 4, pp: 631-635, Anno: 2011

System-Level Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip with Programmable Routing Logic
Ghiribaldi, Alberto; Ludovici, Daniele; Favalli, Michele; Bertozzi, Davide     dettagli >>

Atto di Convegno (Proceedings)
IEEE, IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)
pp: 308-313, Anno: 2011

Exploiting Network-on-Chip Structural Redundancy for A Cooperative and Scalable Built-In Self-Test Architecture
Strano, Alessandro; C. G., Requena; Ludovici, Daniele; M. E., Gomez; Favalli, Michele; Bertozzi, Davide     dettagli >>

Atto di Convegno (Proceedings)
ACM/IEEE, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
pp: 661-666, Anno: 2011

Testing Resistive Opens and Bridging Faults Through Pulse Propagation
Favalli, Michele; C., Metra     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Vol. 28, No. 6, pp: 915-926, Anno: 2009

How many test vectors we need to detect a bridging fault?
Favalli, Michele; M., Dalpasso     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
JOURNAL OF ELECTRONIC TESTING
Vol. 25, No. 1, pp: 79-95, Anno: 2009

Pulse propagation for the detection of small delay defects
Favalli, Michele    

Atto di Convegno (Proceedings)
IEEE - CS Press, DATE'07 (Design Automation and TEst in Europe)
pp: 1-6, Anno: 2007

Delay fault detection problems in circuits featuring a low combinational depth
Favalli, Michele    

Atto di Convegno (Proceedings)
IEEE CS - press, IEEE Defect and Fault Tolerant Symposium in VLSI Systems
pp: 170-178, Anno: 2007

High quality test vectors for bridging faults in the presence of IC's parameters variations
Favalli, Michele; Dalpasso, M.     dettagli >>

Atto di Convegno (Proceedings)
IEEE COMPUTER SOC, IEEE Symposium on Defect and Fault Tolerance in VLSI Systems
pp: 448-456, Anno: 2007

Diversity analysis in the presence of delay faults affecting duplex systems
Favalli, Michele     dettagli >>

Contributo in rivista (Pubblicazione in Rivista)
IEEE TRANSACTIONS ON COMPUTERS
Vol. 55, No. 3, pp: 348-352, Anno: 2006

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