Davide Bertozzi received the PhD degree in Electrical Engineering from University of Bologna in 2003. Since 2005, he is Assistant Professor at University of Ferrara and leads the Multi-Processor System-on-Chip Design group. He was a Visiting Researcher at International Academic Institutions (Stanford University, USA) and Semiconductor Industries (NEC America Labs, USA; NXP Semiconductors, Holland; STMicroelectronics, Italy; Samsung Electronics, Korea). His main research interests concern MPSoC design issues, with emphasis on the communication architecture and on its evolution to an on-chip network. His studies address mainly power and reliability concerns, which are tackled by means of architecture as well as circuit level techniques with layout awareness. He has been program chair of recent events of the network-on-chip community (Int. Symposium on Networsk-on-Chip 2008, IET CDT Special Issue on NoCs 2009). He takes part to the technical program committee of international conferences (e.g., Design and Automation Conference, Int. GLSVLSI Symposium, Int.Symp. on Networks-on-Chip) and scientific journals (IEEE Transactions on VLSI, on CAD of Circuits and Systems, on Computers). He is member of the Editorial Board of the IET Computers and Digital Techniques Journal.
He is involved in the Galaxy FP7 project studying the applicability of the GALS paradigm to NoCs, and in the Hipeac-2 Network-of-Excellence, where he is involved with the activities of the Interconnect Cluster.